(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the profile of Shallow Trench Isolation regions.
(2) Description of the Prior Art
One of the major disciplines that is used for the creation of semiconductor devices is the art of photolithography. Photolithography is used to create patterns of various designs in semiconductor surfaces. An UV or DUV light source is used to project the image of a mask onto a target surface. The target surface typically is a layer of photoresist, the mask that is used between the light source and the target surface contains regions of total light transparency and regions that block all light from passing through the mask. This latter characteristics results in energy (from the light source) being transmitted into the target surface which changes the chemical and molecular properties of the target surface. Photolithography provides a system of one or more optical lenses through which the light passes before striking the target surface. These lenses have as design objective to create the perfect reflection of the image that is contained in the mask onto the surface that is exposed by the light source. Light of the energy source is transmitted to the target surface as waves of a particular frequency, amplitude and phase and as such is subjected to the laws of physics in its passage from source to target. Ideally all the light that strikes the target surface does so under the exact same conditions of frequency, amplitude, phase and angle of impact so that the image that is created in the target surface is uniform across that surface. A serious problem in this respect of the effect of optical diffraction whereby the light that impacts a surface does so under an angle that varies across the target surface. This effect becomes particularly severe where devices are created of micron or sub-micron dimensions, whereby any deviation from an ideal geometry of the created device features has a relatively larger impact. Reduced device feature size also brings with it the requirement for improved image resolution since the adjacency between device features across the surface of a semiconductor surface is likely to decrease with decreasing device feature size. The resolution of the created image on a target surface is essentially determined by the optimum available numerical aperture of the lens system that is used for the image formation. Improving this performance parameter however is in conflict with the desire to achieve optimum depth of focus of the exposed image since the depth of focus of a lens system is inversely proportional with the numerical aperture of the lens system. To provide the required ideal image in a target surface, a number of corrective measures can be used that offset the undesirable characteristics of the system that is used to create this image. These corrective measures can make use of any or a combination of the parameters that play a role in the creation of the ideal image and that essentially already have been highlighted as light amplitude, frequency and phase. In addition, the method in which the image is created can be changed by for instance "predistorting" the image, that is creating an image before the process of exposure occurs that, when the distorting effects of the image formation are taken into account, forms an ideal image on the target surface or at least an image that is as close as possible to the ideal image. It is clear that these corrective measures are highly image dependent in the sense that, across the surface of a relatively large wafer, effects that are applied to the center of the wafer surface may have an entirely different effect at the perimeter of the wafer.
Light diffraction is the modification of light as it passes through opaque surfaces or through narrow slits and in which the light appears to be deflected and produces fringes of parallel light and dark or colored bands of light. The impact that light diffraction has on image formation where the images are of extremely small dimensions (0.5 microns or less) is therefore readily apparent in that light that is meant for a particular (small) areas readily "spills over" in an immediately adjacent (and equally small) area thus preventing sharp definitions of the two adjacent areas.
Phase control of the light that is used to create an image can be implemented by making use of the fact that the phase of the light that exits a surface (such as a photo lithographic mask) can be made to relate to the phase of the light as it enters this surface whereby the parameter of control in adjusting this phase relationship is the thickness of the surface through which the light travels. By varying the thickness of the surface through which the light passes (that is having a surface that is not of uniform thickness) the phase of the light can be changed and therefore the amplitude of the light that exits the surface can be controlled (across the surface of for instance a photolithographic mask). The image that is created in this manner can therefore be adjusted or manipulated to compensate for any negative effects that are present in the imaging system. This latter approach may appear to be complex and difficult to implement were it not for the fact that most image processing systems are highly automated and are computerized to a large extend. The design parameters that affect ultimate image qualities can therefore readily be entered into a computer system where they become part of the appropriate support software and can change imaging rules and behavior for optimum results. A computer based design system also lends itself well to implementing requirements of mask exposure over relatively large surfaces and to make exposures that are dependent on the location within a large surface. This latter capability must be considered a basic requirement for any such automated or computer aided design system since most semiconductor devices are produced using large wafers and are mass produced whereby multiple device features are simultaneously created as part of one exposure sequence.
The process of the invention is aimed at creating Shallow Trench Isolation (STI) regions in a semiconductor surface. STI regions are typically used in creating Field Effect Transistor (FET's) to reduce or eliminate leakage currents between or around the periphery of these devices.
In using the STI approach for the VLSI technology, deep trenches are typically made in the substrate by reactive ion etching. The trenches are typically about 5-6 um. deep, about 2-3 um. wide and spaced about 2.5.-3.5 um. apart from another trench. The ULSI technology requires trenches that are deeper and spaced closer together posing new problems of field turn-on, punchthrough, gap-fill within the trenches and others.
STI's can be made using a variety of methods. For instance, one method is the Buried Oxide (BOX) isolation used for shallow trenches. The method involves filling the trenches with a chemical vapor deposition (CVD) silicon oxide (SiO.sub.2) and then etched back or mechanically or chemically polished to yield a planar surface. The shallow trenches etched for the BOX process are anisotropically plasma etched into the silicon substrate and are typically between 0.5 and 0.8 micrometer (um.) deep. STI are formed around the active device to a depth between 4000 and 20000 Angstrom.
Another approach in forming STI's is to deposit silicon nitride on thermally grown oxide. After deposition of the nitride, a shallow trench is etched into the substrate using a mask. A layer of oxide is then deposited into the trench so that the trench forms an area of insulate dielectric which acts to isolate the devices in a chip and thus reduce the cross talk between active devices. The excess deposited oxide must be polished off and the trench planarized to prepare for the next level of metalization. The silicon nitride is provided to the silicon to prevent polishing of the masked silicon oxide of the device.
While the dielectric-filled trench isolation can provide effective dielectric isolation between devices, it remains a key requirement of the creation of STI regions that the geometry of the STI remains uniform across the surface in which they are created. Lack of uniform geometry of the STI region may result in a structure that tends to be non-planar. This lack of planarity is mainly due to the difference in the amount of fill that is required to fill a multiplicity of closely spaced trenches and the dielectric that is deposited on the surface of the substrate. This effect is further aggravated by the steps of bake and cure that are applied to the deposited dielectric in order to cure the dielectric and to evaporate the solvents from the dielectric. Further problems can be caused in this respect by the fact that in many chip designs there can be a significant difference in device density across the chip. In the design of memory chips for instance, the memory functions of the chip can consist of 10.000 or more memory elements. These memory elements are surrounded by their supporting logic functions which tend to have considerably lower density of active elements thereby further aggravating the problems of even distribution of the deposited dielectric across the surface of the chip and of obtaining good planarization for the entire surface of the chip. It is clear that poor planarity across the surface of the trenches leads to further problems in creating interconnect patterns and in depositing overlying layers of insulation and metalization. These overlying layers of metalization must be patterned and etched, a typically photolithographic process that requires constant and low depth of focus. Where this depth of focus is not as required, wire patterns of poor quality are created resulting a serious yield detractors and concerns of device reliability.
Another problem associated with the formation of STI regions is that, where these STI regions do not have a uniform geometry over the surface of the wafer, if the silicon oxide is etched or polished to the surface of the silicon substrate, dishing occurs in the surface of the silicon oxide resulting in a concave surface of the STI regions. This results in recesses in the field oxide at the edge of the device areas. Later, when the gate electrodes are made for the FET's, the gate electrodes extend over the device area edge, causing an undesirable lower and variable threshold voltage when the devices are completed. It is therefore desirable to make isolation areas that avoid this problem by providing STI's with uniform geometries.
FIG. 1 shows a cross section of an STI region that has well defined edges around the perimeter of the STI region due to a good profile of the STI. An STI region with this profile will perform well with respect to leakage currents and breakdown voltage.
FIG. 2 shows a cross section of an STI region that has poorly defined edges around the perimeter of the STI region due to a poor profile of the STI. An STI region with this profile will perform not well with respect to leakage currents and breakdown voltage.
Various approaches have been taken in the prior art to deal with the proximity effect. Eisenberg et al (U.S. Pat. No. 5,057,462 dated October 1991) examines the results of a first pass attempt and then modify the etching and resist parameters accordingly. Borodovsky et al. (U.S. Pat. No. 5,498,579, dated March 1996) use two masks, the second one serving to compensate for proximity effects introduced by the first one. Liebmann (U.S. Pat. No. 5,553,273, dated September 1996) sorts a design into small areas according to shape and width and those areas that are identified as gate regions are biased based on applicable OPC rules. Maehara (U.S. Pat. No. 5,375,157, dated December 1994) teaches the manufacture of a distortion free mask for X-ray lithography. Chung et al. (U.S. Pat. No. 5,432,714, dated July 1995) shows how accumulated information on exposure can be used during electron beam lithography to compensate for proximity effects. Further Prior Art patents are listed below.
U.S. Pat. No. 5,567,553 (Hsu et al.) shows a method to reduce leakage due to sharp isolation corners (OD).
U.S. Pat. No. 5,766,806 (Spence) teaches an optical lithography using PSM.
U.S. Pat. No. 5,858,591 (Lin et al.) shows an OPC through subfile bias modification with subsequent subfile merging.
The process of the invention is aimed at the existing problem of lack of uniformity of the STI geometry across the surface of the substrate in which the STI regions are formed.